But I got to play around with EPFL's focused ion beam (FIB) for another project. EPFL's FIB is a combination of an electron microscope, a platinum depositor, and a Gallium microscope/etcher.
What was I doing with the FIB? I was fixing integrated circuits. One fixes circuits by etching away parts of the chip (the equivalent of cutting a line), and then using the platinum depositor to short other lines. This re-routes the signals, and fixes your design mistake. The etching is performed by the Ga microscope. Normally the number of Ga ions does not drastically effect the surface, but if you use a lot of Ga ions, then you can etch away parts of the chip. The etching occurs even when you're using the Ga microscope as a microscope - in other words, if you use the microscope for too long, you etch away the entire surface off the chip. As far as I know electron microscopes don't have sufficient energy to etch the surface, but it wouldn't surprise me if a high-energy electron microscope could also etch a chip.
The etching is mechanical, so the etched atoms spray above the chip. The etching is performed in a vacuum so that these atoms don't (hopefully don't) end up on the surface of the chip and interfere with surface electronics.
Anyways, that is enough theory. One of the other groups has been having trouble properly simulating a design, so they wanted to use the FIB at EPFL to test something. Since I was going to be in Switzerland, I oversaw the FIB use.
A high level overview is that we needed to re-route a grounded signal. A line was shorted to ground, and we needed to short it to the power rail instead. I'll call the line we're working with line "Q". First, we had to cut line Q. Next, we exposed line Q a distance away. We then exposed the power line. Finally, we shorted line Q's exposure to the power line's exposure. Well, at least we think we did. No one has tested the chips yet.
You might ask yourself why we didn't just short the power line to line Q's cut directly. The platinum (Pt) deposition isn't easily controlled (we're working with nanometers of distance), and we would have risked shorting both sides of the cut to the power rail if we tried to short the power rail to Q at the cut. Risking a power rail to ground short is bad. Very bad.
First up, we cut line Q. Here is a picture:
The hole near the bottom-middle of the L-shaped objects is the cut. I believe the L-shaped and square objects are support patterns on the surface of the chip. Silicon foundries yell at you if you don't use a minimum amount of metal for each layer. Something like a third of the layer must be used. I'm not sure if it is an issue with the lower layers supporting the upper layers or the implant process, but either way it is easier to put patterns on the un-used parts of the chip than having the foundry yell at you. You can see some lower layer patterns in the cut, they're the twelve or so little dots. We use different patterns for different layers, ostensibly for better chip support. Or something. I'm not 100% sure about reasons behind the patterns, so take everything I saw about them with a grain of salt.
Anyways, next up we needed to expose the Q line farther down:
I've circled the exposed Q line, which runs vertically. Ga ions interact differently with conductors, and the results is that conductors show up more brightly in pictures from this Ga microscope. If this pictures doesn't convince you that we hit the line, I wasn't convinced either. Due to the support patterns, the Ga ions etch through the chip at different speeds, and it was impossible to get a picture-perfect exposure. Also, please keep in mind that the line is about 500 nm wide. This was the best result of several failed attempts on previous chips.
Similarly, we found the power supply line, which ran horizontally:
Finally, we used the Pt depositor to short the two:
As you can see, some of the surface material was sucked into the hole when we deposited the Pt bypass. I don't know if the material melted or was pulled down from a mechanical force.
As I previously said, we haven't tested these chips. Even if they don't work, it was a very interesting event to see. Please feel free to ask any questions, though I'm not sure I'll be able to answer them. Single bypass surgery on integrated circuits isn't my specialty.
5 comments:
Cool post. I've never done FIB, but one of my apartment mates is doing her masters thesis on a FIB project. TEMs don't generally damage the sample, but it depends on the material & how much time you spend looking at a particular spot- the sample can react to the beam, but it's not really a direct etching process.
But this is all to fix a design flaw? I am curious, I was under the impression that having a chip made was not huge deal- you draw the schematic, you send it away. Is it expensive? Is it better/most cost effective to travel to Lausanne to use the FIB? I'd be interested to know how it works out, from what I hear from the apartment mate, FIB can be kind of hit or miss...(no pun intended)
I think the issue is cost. Producing chips of this area starts at a few thousand euros, whereas the FIB was free for us (yay academic inanity), meaning the only cost was part of a flight (I did other stuff in Lausanne) and hotel.
Oh. Huh. I had no idea that chip production was so expensive.
Augh, I had a nice comment typed out and blogspot ate it!
Anyways, we just taped out a small, 90 nm chip. It was roughly 5K dollars for 100 chips. That should give you a good window for cost. I'm actually not sure what process these chips are on, but I know they're pretty big (area-wise, not process size-wise).
Wow, this is a cool post. Thanks for the pictures. I was expecting to see a Jenn comment when I clicked on the comments button too. Anyway, you can rest assured that the things you waste time on during your experimental research are much cooler than the things I waste my time on.
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